Now a days high speed processors used everywhere. Which require multiple power supplies that generate different core voltages and I/O voltages itself. So there is proper ordering of power supplies to up and down the device, this is mandatory for proper device operation & long term reliability.This note shows some of power sequencing requirements.
- Improper power sequencing to device may occur immediate fault in device or sacrificed it's long term reliability.
- When an active power supply & inactive power supply is fed to device, can stress electrostatic discharge protection and other interfaced which deal with different voltages.
- When designing with multi-power supply logic, timing interval between IO voltages & core voltages during its power ON/OFF condition should be given. During designing this kind of logic, each power supply is isolated by structure which may break (means become forward bias and conduct when it's not suppose to be!!) when supplies are not in sequence.
- Power sequencing is require "To avoid system level bus contention"
- Some time I/O power supplies and peripherals power supplies are connected a common points. So when core voltage & I/O voltages applied at same time, some of data from peripherals come to processor & processor data goes to peripherals on same bi-directional bus which may oppose each other.
- "To avoid Latch up problem"
- CMOS technology is used to fabricate most multi voltages devices & chips.
- Latch up occur when output voltage of CMOS drops below ground level due to undesired noise spike or an improper circuit hookup.
- Due to this insufficient current flow inside CMOS, it'll create low resistance path and it'll conduct current.
- Only way to stop it is to reduce current below circuit level. This can be achieve by removing power from device only.
- To avoid latch up problem, provide proper power sequence is advisable.
- Most likely this problem occurs in pad drives when large voltage transients with large amount of current.
- Some processors support both sequence, IO power supplies before core supplies & Core supplies before IO power supplies. Power sequencing can be achieve using power sequencer ICs and power management ICs.
Recommendation is 100 ms between one power supply rail valid and next power supply rail in sequence starting to ramp.
Every processor designer provide power sequence in its datasheet. Keep RESET signal low during power sequencing.
Hi Kuldeep, the information is very useful to me. And I have one doubt please clear this...
ReplyDeletewhat means active power supply and inactive power supply?
The main difference between active power supply and passive power supply is the use of components used while designing power supply.
DeleteIf power supply is designed using mostly active components it will be active power supply. Similar to passive power supply.